Renesas RX Series User Manual

R01UH0823EJ0100 Rev.1.00 Page 759 of 1823
Jul 31, 2019
RX23W Group 27. Compare Match Timer (CMT)
27.4 Interrupts
27.4.1 Interrupt Sources
The CMT has channels and each of them to which a different vector address is allocated has a compare match interrupt
(CMIn) (n = 0 to 3). When a compare match interrupt occurs, the corresponding interrupt request is output.
When the interrupt request is used to generate a CPU interrupt, the priority of channels can be changed by the interrupt
controller settings. For details, see
section 15, Interrupt Controller (ICUb).
27.4.2 Timing of Compare Match Interrupt Generation
When the CMCNT counter and the CMCOR register match, a compare match interrupt (CMIn) (n = 0 to 3) is generated.
A compare match signal is generated at the last state in which the values match (the timing when the CMCNT counter
updates the matched count value). That is, after a match between the CMCOR register and the CMCNT counter, the
compare match signal is not generated until the next the CMCNT counter input clock.
Figure 27.4 shows the timing of a compare match interrupt.
Figure 27.4 Timing of a Compare Match Interrupt
Table 27.2 CMT Interrupt Sources
Name Interrupt Sources DTC Activation DMAC Activation
CMI0 Compare match in CMT0 Possible Possible
CMI1 Compare match in CMT1 Possible Possible
CMI2 Compare match in CMT2 Possible Possible
CMI3 Compare match in CMT3 Possible Possible
PCLK
CMCNT input clock
CMCNT
CMCOR
Interrupt request
(edge)
N
N
0
Compare match signal

Renesas RX Series Specifications

General

Core	RXv1, RXv2, RXv3
Flash Memory	Up to 8 MB
RAM	Up to 1 MB
Operating Voltage	1.62V to 5.5V
Operating Temperature	-40°C to +85°C or +105°C
Package	BGA, LQFP
ADC Resolution	12-bit
DAC Resolution	12-bit
Communication Interfaces	SCI, SPI, I2C, USB, Ethernet, CAN
Architecture	32-bit
Security Features	Memory Protection Unit (MPU)