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Renesas RX Series User Manual

Renesas RX Series
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R01UH0823EJ0100 Rev.1.00 Page 942 of 1823
Jul 31, 2019
RX23W Group 32. USB 2.0 Host/Function Module (USBc)
32.3.5.4 DMA Transfers (D0FIFO and D1FIFO Ports)
(1) Overview of DMA Transfers
For PIPE1 to PIPE9, the FIFO port can be accessed using the DMAC. When accessing the buffer for the pipe targeted for
DMA transfer is enabled, a DMA transfer request is issued.
The unit of transfer to the FIFO port should be selected using the DnFIFOSEL.MBW bit and the pipe targeted for the
DMA transfer should be selected using the DnFIFOSEL.CURPIPE[3:0] bits. The selected pipe should not be changed
during the DMA transfer.
(2) DnFIFO Auto Clear Mode (D0FIFO and D1FIFO Port Reading Direction)
If 1 is set in the DnFIFOSEL.DCLRM bit, the USB automatically clears the buffer memory of the selected pipe when
reading of data from the buffer memory has been completed.
Table 32.21 shows the packet reception and buffer memory clearing processing by software for each of the various
settings. As shown in
Table 32.21, the buffer clearing conditions depend on the value set in the PIPECFG.BFRE bit.
Using the DnFIFOSEL.DCLRM bit eliminates the need for the buffer to be cleared by software in any situation that
requires buffer clearing. This enables DMA transfers without involving software.
The DnFIFO auto clear mode can be set only in the buffer memory reading direction.
Table 32.21 Packet Reception and Buffer Memory Clearing Processing by Software
Buffer Status
When Packet is Received
Register Setting
DCLRM = 0 DCLRM = 1
BFRE = 0 BFRE = 1 BFRE = 0 BFRE = 1
Buffer full Clearing is not
necessary
Clearing is not
necessary
Clearing is not
necessary
Clearing is not
necessary
Zero-length packet reception Clearing is necessary Clearing is necessary Clearing is not
necessary
Clearing is not
necessary
Normal short packet reception Clearing is not
necessary
Clearing is necessary Clearing is not
necessary
Clearing is not
necessary
Transaction count end Clearing is not
necessary
Clearing is necessary Clearing is not
necessary
Clearing is not
necessary

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Renesas RX Series Specifications

General IconGeneral
CoreRXv1, RXv2, RXv3
Flash MemoryUp to 8 MB
RAMUp to 1 MB
Operating Voltage1.62V to 5.5V
Operating Temperature-40°C to +85°C or +105°C
PackageBGA, LQFP
ADC Resolution12-bit
DAC Resolution12-bit
Communication InterfacesSCI, SPI, I2C, USB, Ethernet, CAN
Architecture32-bit
Security FeaturesMemory Protection Unit (MPU)

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