Renesas RX Series User Manual

R01UH0823EJ0100 Rev.1.00 Page 1371 of 1823
Jul 31, 2019
RX23W Group 38. Serial Peripheral Interface (RSPIa)
38.3.4.2 When Parity is Enabled (SPCR2.SPPE = 1)
When parity is enabled, the lowest-order bit of the data for transmission becomes a parity bit. Hardware calculates the
value of the parity bit.
(1) MSB First Transfer (32-Bit Data)
Figure 38.18 shows details of operations by the RSPI data register (SPDR) and the shift register in transfer with parity
enabled, an RSPI data length of 32 bits, and MSB first selected.
In transmission, the value of the parity bit (P) is calculated from bits T31 to T01. This replaces the final bit, T00, and the
whole is copied to the shift register. Data are transmitted in the order T31, T30, …, T01, and P.
In reception, received data are shifted in bit by bit through bit 0 of the shift register. When bits R31 to P have been
collected after input of the required number of cycles of RSPCK, the value in the shift register is copied to the receive
buffer. On copying of data to the shift register, the data from R31 to P are checked by judging the parity.
Figure 38.18 MSB First Transfer (32-Bit Data, Parity Enabled)
Bit 31
Transfer start
Transfer end
Bit 0
T31 T30 T29 T28 T27 T26 T25 T24 T23 T06 T05 T04 T03 T02 T01 T00
T31 T30 T29 T28 T27 T26 T25 T24 T23 T06 T05 T04 T03 T02 T01 P
R31 R30 R29 R28 R27 R26 R25 R24 R23 R06 R05 R04 R03 R02 R01 P
R31 R30 R29 R28 R27 R26 R25 R24 R23 R06 R05
T08 T07
T08 T07
R08 R07
R08 R07 R04 R03 R02 R01 P
Transmit buffer
Shift register
Copy
Shift register
Input
Output
Copy
Bit 0
Bit 0
Bit 0
Receive buffer
Bit 31
Bit 31
Bit 31
T31 T30 T29 T28 T27 T26 T25 T24 T23 T06 T05 T04 T03 T02 T01 P
T08 T07
Copy
Parity calculated
Parity added
Note: Output = MOSI (master)/MISO (slave), input = MISO (master)/MOSI (slave)

Renesas RX Series Specifications

General

Brand	Renesas
Model	RX Series
Category	Microcontrollers
Language	English