R01UH0823EJ0100 Rev.1.00 Page 1370 of 1823
Jul 31, 2019
RX23W Group 38. Serial Peripheral Interface (RSPIa)
(4) LSB First Transfer (24-Bit Data)
Figure 38.17 shows details of operations by the RSPI data register (SPDR) and the shift register in transfer with parity
disabled, 24 bits as the RSPI data length for an example that is not 32 bits, and LSB first selected.
In transmission, the lower-order 24 bits (T23 to T00) from the current stage of the transmit buffer are reordered bit by bit
to obtain the order T00 to T23 for copying to the shift register. Data for transmission are shifted out from the shift register
in order from T00, through T01, and so on to T23.
In reception, received data are shifted in bit by bit through bit 8 of the shift register. When bits R00 to R23 have been
collected after input of the required number of cycles of RSPCK, the value in the shift register is copied to the receive
buffer.
At this time, the higher-order 8 bits of the transmit buffer are stored in the higher-order 8 bits of the receive buffer.
Writing 0 to bits T31 to T24 at the time of transmission leads to 0 being inserted in the higher-order 8 bits of the receive
buffer.
Figure 38.17 LSB First Transfer (24-Bit Data, Parity Disabled)
R00 R01 R02 R03 R04 R05 R06 R07 R08 T25 T26 T27 T28 T29 T30 T31
T31 T30 T29 T28 T27 T26 T25 T24 R23 R06 R05
R23 T24
R08 R07 R04 R03 R02 R01 R00
Input
Transfer start
Transfer end
Bit 31 Bit 0
T31 T30 T29 T28 T27 T26 T25 T24 T23 T06 T05 T04 T03 T02 T01 T00
T00 T01 T02 T03 T04 T05 T06 T07 T08 T25 T26 T27 T28 T29 T30 T31
T08 T07
T23 T24
Receive buffer
Transmit buffer
Shift register
Shift register
Output
Copy
Copy
Bit 31 Bit 0
Bit 31 Bit 0
Bit 31 Bit 0
Note: Output = MOSI (master)/MISO (slave), input = MISO (master)/MOSI (slave)
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