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R01UH0823EJ0100 Rev.1.00 Page 1369 of 1823

Jul 31, 2019

RX23W Group 38. Serial Peripheral Interface (RSPIa)

(3) LSB First Transfer (32-Bit Data)

Figure 38.16 shows details of operations by the RSPI data register (SPDR) and the shift register in transfer with parity

disabled, an RSPI data length of 32 bits, and LSB first selected.

In transmission, bits T31 to T00 from the current stage of the transmit buffer are reordered bit by bit to obtain the order

T00 to T31 for copying to the shift register. Data for transmission are shifted out from the shift register in order from

T00, through T01, and so on to T31.

In reception, received data are shifted in bit by bit through bit 0 of the shift register. When bits R00 to R31 have been

collected after input of the required number of cycles of RSPCK, the value in the shift register is copied to the receive

buffer.

Figure 38.16 LSB First Transfer (32-Bit Data, Parity Disabled)

Transfer start

Transfer end

T31 T30 T29 T28 T27 T26 T25 T24 T23 T06 T05 T04 T03 T02 T01 T00

T00 T01 T02 T03 T04 T05 T06 T07 T08 T25 T26 T27 T28 T29 T30 T31

R00 R01 R02 R03 R04 R05 R06 R07 R08 R25 R26 R27 R28 R29 R30 R31

R31 R30 R29 R28 R27 R26 R25 R24 R23 R06 R05

R23 R24

R08R07 R04R03R02R01R00

T08 T07

T23 T24

Shift register

Input

Output

Copy

Bit 0

Receive buffer

Bit 31

Transmit buffer

Bit 0Bit 31

Note: Output = MOSI (master)/MISO (slave), input = MISO (master)/MOSI (slave)

Renesas RX Series User Manual

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