Renesas RX Series User Manual

R01UH0823EJ0100 Rev.1.00 Page 307 of 1823
Jul 31, 2019
RX23W Group 16. Buses
16.2 Description of Buses
16.2.1 CPU Buses
The CPU buses consist of the instruction and operand buses, which are connected to internal main bus 1. As the names
suggest, the instruction bus is used to fetch instructions for the CPU, while the operand bus is used for operand access.
The instruction bus is 64 bits while the operand bus is 32 bits.
Connection of the instruction and operand buses to RAM and ROM provides the CPU with direct access to these areas,
i.e. access is not via internal main bus 1. However, only reading is possible in direct access to ROM by the CPU;
programming and erasure are handled via an internal peripheral bus.
Bus requests for instruction fetching and operand access are arbitrated through internal main bus 1. The order of priority
is operand access then instruction fetching.
If instruction fetching and operand access are requested for different buses (memory bus 1, memory bus 2, and internal
main bus 1), the bus-access operations can proceed simultaneously. For example, parallel access to ROM and RAM is
possible.
16.2.2 Memory Buses
The memory buses consist of memory bus 1 and memory bus 2. RAM is connected to memory bus 1 and ROM is
connected to memory bus 2. The memory buses are 64 bits. Requests for bus mastership from the CPU buses (instruction
fetching and operand) and internal main bus 2 are arbitrated through memory buses 1 and 2.
The priority order of the buses can be set using the memory bus 1 (RAM) priority control bits (BPRA[1:0]) and memory
bus 2 (ROM) priority control bits (BPRO[1:0]) in the bus priority control register (BUSPRI) for the corresponding
memory buses. When the priority order is fixed, internal main bus 2 has priority over the CPU bus (operand over
instruction fetching). When the priority order is toggled, a bus has a lower priority when the request of that bus is
accepted.
16.2.3 Internal Main Buses
The internal main buses consist of a bus for use by the CPU (internal main bus 1) and a bus for use by the other
bus-master modules, i.e. the DTC and DMAC (internal main bus 2).
Bus requests for instruction fetching and operand access are arbitrated through internal main bus 1. The order of priority
is operand access then instruction fetching.
Requests for bus mastership from the DTC and DMAC are arbitrated by internal main bus 2. The priority order is the
DMAC and then DTC as listed in
Table 16.3.
Between the DTC and DMAC, only the one that accepted the activation request issues the bus mastership request. The
priority order of activation requests between the DTC and DMAC is DMAC0, DMAC1, DMAC2, DMAC3, and then
DTC, regardless of the BUSPRI setting.
If the CPU and another bus master are requesting access to different buses (on-chip memory, internal peripheral buses 1
to 4, and 6), the respective bus-access operations can proceed simultaneously.
However, when the CPU executes the XCHG instruction, requests for bus access from masters other than the CPU are
not accepted until data transfer for the XCHG instruction is completed regardless of the bus priority control register
(BUSPRI) setting. Furthermore, requests for bus access from masters other than the DTC are not accepted during reading
and writing-back of transfer control information for the DTC.

Renesas RX Series Specifications

General

Brand	Renesas
Model	RX Series
Category	Microcontrollers
Language	English