Renesas RX Series User Manual

R01UH0823EJ0100 Rev.1.00 Page 691 of 1823
Jul 31, 2019
RX23W Group 25. 16-Bit Timer Pulse Unit (TPUa)
25.3.3 Buffer Operation
Buffer operation, provided for TPU0 and TPU3, enables TPUm.TGRC and TPUm.TGRD to be used as buffer registers.
Buffer operation differs depending on whether TPUm.TGRy has been set as an input capture register or a compare match
register.
Table 25.20 lists the register combinations used in buffer operation.
 When TPUm.TGRy is an output compare register
When a compare match occurs, the value in the buffer register for the corresponding channel is transferred to the timer
general register.
This operation is shown in
Figure 25.12.
Figure 25.12 Compare Match Buffer Operation
 When TPUm.TGRy is an input capture register
When input capture occurs, the value in TPUm.TCNT is transferred to TGRy and the value previously held in TGRy is
simultaneously transferred to the buffer register.
This operation is shown in
Figure 25.13.
Figure 25.13 Input Capture Buffer Operation
Table 25.20 Register Combinations
Channel Timer General Register Buffer Register
TPU0 TPU0.TGRA TPU0.TGRC
TPU0.TGRB TPU0.TGRD
TPU3 TPU3.TGRA TPU3.TGRC
TPU3.TGRB TPU3.TGRD
Buffer register Comparator TCNT
Compare match signal
Timer general
register
Input capture
signal
Buffer register TCNT
Timer general
register

Renesas RX Series Specifications

General

Brand	Renesas
Model	RX Series
Category	Microcontrollers
Language	English