Renesas RX Series User Manual

R01UH0823EJ0100 Rev.1.00 Page 599 of 1823
Jul 31, 2019
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a)
23.6.8 Contention between Buffer Register Write and TCNT Clear Operations
When the buffer transfer timing is set at the TCNT clear timing by the timer buffer operation transfer mode register
(TBTM), if TCNT clearing occurs in a TGR write cycle, the data before write operation is transferred to TGR by the
buffer operation.
Figure 23.101 shows the timing in this case.
Figure 23.101 Contention between Buffer Register Write and TCNT Clear Operations
23.6.9 Contention between TGR Read Operation and Input Capture
If an input capture signal is generated in a TGR read cycle, the data before input capture transfer is read.
Figure 23.102 shows the timing in this case.
Figure 23.102 Contention between TGR Read Operation and Input Capture (MTU0 to MTU4)
Buffer transfer signal
TGR
N
NM
PCLK
Written by CPU
Buffer register
TCNT clear signal
Buffer register write data
Internal data bus
PCLK
Input capture signal
TGR
Read by CPU
N
NM

Renesas RX Series Specifications

General

Brand	Renesas
Model	RX Series
Category	Microcontrollers
Language	English