R01UH0823EJ0100 Rev.1.00 Page 656 of 1823
Jul 31, 2019
RX23W Group 24. Port Output Enable 2 (POE2a)
24.4 Interrupts
The POE issues a request to generate an interrupt when the corresponding condition below is matched during input-level
detection, output-level comparison, or oscillation stop by the clock generation circuit.
Table 24.4 lists the interrupt
sources and their request conditions. On acceptance of an OEI1 or OEI2 interrupt, the first line of the exception handling
routine for the given interrupt should confirm that the flag for the given flag has been set to 1.
24.5 Usage Notes
24.5.1 Transitions to Software Standby Mode
When the POE is used, do not make a transition to software standby mode. In this mode, the POE stops and thus the
high-impedance of pins cannot be controlled.
24.5.2 When the POE Is Not Used
When the POE is not used, write 00h to port output enable control registers 1 and 2 (POECR1 and POECR2),
respectively.
24.5.3 Specifying Pins Corresponding to the MTU
The POE controls high-impedance outputs only when a pin has been specified so that the pin corresponds to the MTU by
setting the PMR and PmnPFS registers. When the pin has been specified as a general I/O pin, the POE does not control
high-impedance outputs.
24.5.4 Notes on High-Impedance Control by Event Signal Reception from the ELC
When writing 0 to the SPOER.CH34HIZ or SPOER.CH0HIZ bit and receiving an event signal conflict, the event signal
takes priority and the corresponding bit is set to 1. If the MTU complementary PWM output and MTU0 pins are placed
in the high-impedance state when an event signal is received from the ELC, no interrupt request is generated.
Table 24.4 Interrupt Sources and Conditions
Name Interrupt Source Interrupt Flag Condition
OEI1 Output enable interrupt 1 POE0F, POE1F, POE3F,
OSF1
When ICSR1.POE0F, POE1F, or POE3F flag is set to 1 with
ICSR1.PIE1 set to 1, or when OCSR1.OSF1 flag is set to 1
with OCSR1.OIE1 set to 1.
OEI2 Output enable interrupt 2 POE8F When ICSR2.POE8F flag is set to 1 with ICSR2.PIE2 set to 1.
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