R01UH0823EJ0100 Rev.1.00 Page 514 of 1823
Jul 31, 2019
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a)
23.2.27 Timer Buffer Transfer Set Registers (TBTER)
The TBTER registers enable or disable transfer from the buffer registers used in complementary PWM mode to the
temporary registers and specify whether to link the transfer with interrupt skipping operation.
Note: Target buffer registers: MTU3.TGRC, MTU3.TGRD, MTU4.TGRC, MTU4.TGRD, and MTU.TCBR
Note 1. Data is transferred in accordance with the TMDR.MD[3:0] bit setting. For details, refer to section 23.3.8, Complementary PWM
Mode.
Note 2. When interrupt skipping is disabled (the TITCR.T3AEN and T4VEN bits or the interrupt skipping count setting bits (T3ACOR[2:0]
and T4VCOR[2:0]) in the TITCR register are set to 000b), be sure to disable link of buffer transfer with interrupt skipping (set the
TBTER.BTE[1] bit to 0).
If link with interrupt skipping is enabled while interrupt skipping is disabled, buffer transfer will not be performed.
Address(es): MTU.TBTER 000D 0A32h
b7 b6 b5 b4 b3 b2 b1 b0
—————— BTE[1:0]
Value after reset:
00000000
Bit Symbol Bit Name Description R/W
b1, b0 BTE[1:0] Buffer Transfer Disable and
Interrupt Skipping Link Setting
These bits enable or disable transfer from the buffer registers used
in complementary PWM mode to the temporary registers and
specify whether to link the transfer with interrupt skipping operation.
Refer to Table 23.39 for details.
R/W
b7 to b2 — Reserved These bits are read as 0. The write value should be 0. R/W
Table 23.39 Setting of TBTER.BTE[1:0] Bits
Bit 1 Bit 0
DescriptionBTE[1] BTE[0]
0 0 Enables transfer from the buffer registers to the temporary registers*
1
and does not link the
transfer with interrupt skipping operation.
0 1 Disables transfer from the buffer registers to the temporary registers.
1 0 Links transfer from the buffer registers to the temporary registers with interrupt skipping
operation.*
2
1 1 Setting prohibited
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