Renesas RX Series User Manual

R01UH0823EJ0100 Rev.1.00 Page 448 of 1823
Jul 31, 2019
RX23W Group 21. I/O Ports
21.3.8 Drive Capacity Control Register (DSCR)
m = 1 to 3, B to E, J
The bit corresponding to a pin with the fixed drive capacity can be read from or written to. However, the drive capacity
cannot be changed.
When high-drive output is selected, switching noise increases compared to when normal output is selected. Carefully
evaluate the effect of noise on the MCU caused by adjacent pins before selecting high-drive output.
The bit corresponding to a pin that does not exist is reserved. A reserved bit is read as 0. The write value should be 0.
Address(es): PORT1.DSCR 0008 C0E1h, PORT2.DSCR 0008 C0E2h, PORT3.DSCR 0008 C0E3h, PORTB.DSCR 0008 C0EBh,
PORTC.DSCR 0008 C0ECh, PORTD.DSCR 0008 C0EDh, PORTE.DSCR 0008 C0EEh, PORTJ.DSCR 0008 C0F2h
b7 b6 b5 b4 b3 b2 b1 b0
B7 B6 B5 B4 B3 B2 B1 B0
Value after reset:
00000000
Bit Symbol Bit Name Description R/W
b0 B0 Pm0 Drive Capacity Control 0: Normal drive output
1: High-drive output
R/W
b1 B1 Pm1 Drive Capacity Control R/W
b2 B2 Pm2 Drive Capacity Control R/W
b3 B3 Pm3 Drive Capacity Control R/W
b4 B4 Pm4 Drive Capacity Control R/W
b5 B5 Pm5 Drive Capacity Control R/W
b6 B6 Pm6 Drive Capacity Control R/W
b7 B7 Pm7 Drive Capacity Control R/W

Renesas RX Series Specifications

General

Core	RXv1, RXv2, RXv3
Flash Memory	Up to 8 MB
RAM	Up to 1 MB
Operating Voltage	1.62V to 5.5V
Operating Temperature	-40°C to +85°C or +105°C
Package	BGA, LQFP
ADC Resolution	12-bit
DAC Resolution	12-bit
Communication Interfaces	SCI, SPI, I2C, USB, Ethernet, CAN
Architecture	32-bit
Security Features	Memory Protection Unit (MPU)