R01UH0823EJ0100 Rev.1.00 Page 940 of 1823
Jul 31, 2019
RX23W Group 32. USB 2.0 Host/Function Module (USBc)
32.3.5.2 FIFO Buffer Clearing
Table 32.18 shows the clearing of the FIFO buffer memory by the USB. The buffer memory can be cleared using the
BCLR, DnFIFOSEL.DCLRM, and PIPEnCTR.ACLRM bit in the port control register.
Either a single or double buffer configuration can be selected for PIPE1 to PIPE5, using the PIPECFG.DBLB bit.
(1) Auto Buffer Clear Mode Function
With the USB, all received data packets are discarded if the PIPEnCTR.ACLRM bit is set to 1. If a correct data packet
has been received, the ACK response is returned to the host controller. The auto buffer clear mode function can be set
only in the buffer memory reading direction.
If the ACLRM bit is set to 1 and then to 0, the buffer memory of the selected pipe can be cleared regardless of the access
direction.
An access cycle of at least 100 ns is required for the internal hardware sequence processing time between ACLRM = 1
and ACLRM = 0.
Table 32.17 Buffer Status Indicated by the INBUFM Flag
DIR INBUFM Buffer Memory Status
0 (receiving direction) Invalid Invalid
1 (transmitting direction) 0 The transmission has been completed.
There is no waiting data to be transmitted.
1 (transmitting direction) 1 The FIFO port has written data to the buffer.
There is data to be transmitted.
Table 32.18 List of Buffer Clearing Methods
FIFO Buffer
Clearing Mode
Clearing Buffer Memory on
CPU Side
Mode for Automatically Clearing
Buffer Memory after Reading
Specified Pipe Data
Auto Buffer Clear Mode for
Discarding All Received Packets
Register used CFIFOCTR
DnFIFOCTR
DnFIFOSEL PIPEnCTR
Bit used BCLR DCLRM ACLRM
Clearing condition Cleared by writing 1 1: Mode valid
0: Mode invalid
1: Mode valid
0: Mode invalid
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