Renesas RX Series User Manual

R01UH0823EJ0100 Rev.1.00 Page 962 of 1823
Jul 31, 2019
RX23W Group 33. Serial Communications Interface (SCIg, SCIh)
33. Serial Communications Interface (SCIg, SCIh)
This MCU has four independent serial communications interface (SCI) channels. The SCI consists of the SCIg module
(SCI1, SCI5, and SCI8) and the SCIh module (SCI12).
The SCIg module (SCI1, SCI5, and SCI8) can handle both asynchronous and clock synchronous serial communications.
Asynchronous serial data communications can be carried out with standard asynchronous communications chips such as
a Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous Communications Interface Adapter (ACIA).
As an extended function in asynchronous communications mode, the SCI also supports smart card (IC card) interfaces
conforming to ISO/IEC 7816-3 (standard for Identification Cards). The SCI is also supports simple SPI interfaces, and
simple I
2
C-bus interfaces when configured for single-master systems.
The SCIh module includes the functions of the SCIg module, and supports an extended serial communication protocol
formed of Start Frames and Information Frames.
In this section, “PCLK” is used to refer to PCLKB.
33.1 Overview
Table 33.1 lists the specifications of the SCIg module, Table 33.2 lists the specifications of the SCIh module, and
Table 33.3 lists the specifications of the individual SCI channels.
Figure 33.1 shows the block diagram of SCI1 and SCI8, Figure 33.2 shows the block diagram of SCI5, and Figure
33.3
shows the block diagram of SCI12 (SCIh).
Table 33.1 SCIg Specifications (1/2)
Item Description
Serial communication modes  Asynchronous
 Clock synchronous
 Smart card interface
 Simple I
2
C-bus
 Simple SPI bus
Transfer speed Bit rate specifiable with the on-chip baud rate generator.
Full-duplex communications Transmitter: Continuous transmission possible using double-buffer structure.
Receiver: Continuous reception possible using double-buffer structure.
I/O pins Refer to Table 33.4 to Table 33.6.
Data transfer Selectable as LSB first or MSB first transfer*
1
Interrupt sources Transmit end, transmit data empty, receive data full, and receive error
Completion of generation of a start condition, restart condition, or stop condition (for
simple I
2
C mode)
Low power consumption function Module stop state can be set for each channel.
Asynchronous mode Data length 7, 8, or 9 bits
Transmission stop bit 1 or 2 bits
Parity Even parity, odd parity, or no parity
Receive error detection Parity, overrun, and framing errors
Hardware flow control CTSn# and RTSn# pins can be used in controlling transmission/reception.
Start-bit detection Low level or falling edge is selectable.
Break detection When a framing error occurs, a break can be detected by reading the RXDn pin
level directly.
Clock source An internal or external clock can be selected.
Transfer rate clock input from the TMR can be used. (SCI5)
Double-speed mode Baud rate generator double-speed mode is selectable.
Multi-processor
communications function
Serial communication among multiple processors
Noise cancellation The signal paths from input on the RXDn pins incorporate digital noise filters.

Renesas RX Series Specifications

General

Brand	Renesas
Model	RX Series
Category	Microcontrollers
Language	English