R01UH0823EJ0100 Rev.1.00 Page 1669 of 1823
Jul 31, 2019
RX23W Group 50. Flash Memory (FLASH)
50.4.9 Flash Control Register (FCR)
Note 1. This does not include set the FCR register to 00h when the FSTATR1.FRDY flag is 1.
Data can be written to the FCR register when in ROM P/E mode and the ROM can be programmed/erased or in E2
DataFlash P/E mode.
This register is initialized by a reset or setting the FRESETR.FRESET bit to 1. Data cannot be written to this register
while the FRESETR.FRESET bit is 1.
Note that this register cannot be initialized by the FRESETR.FRESET bit while a software command is being executed.
CMD[3:0] Bits (Software Command Setting)
These bits are used to set a software command (program, blank check, block erase, or all-block erase).
The function of each command is described below.
[Program]
Write the value set in registers FWB0, FWB1, FWB2, and FWB3 to the address set in registers FSARH and
FSARL.
[Blank check]
Check whether there is data in the area from the address set in registers FSARH and FSARL to the address set in
registers FEARH and FEARL. Confirm that data is not programmed in the area. This command does not guarantee
whether the area remains erased.
[Block erase]
Erase consecutive areas specified in the flash memory by the blocks. Set the beginning address of the block in
registers FSARH and FSARL and the end address in registers FEARH and FEARL.
[All-block erase]
Erase all blocks in the ROM or E2 DataFlash.
All-block erase requires less time to erase the memory compared to block erase. When erasing the whole of the
ROM area, set the beginning address of the ROM area in registers FSARH and FSARL, and the end address in
registers FEARH and FEARL.
Table 50.4 lists the setting address for all-block erase.
Address(es): FLASH.FCR 007F C114h
b7 b6 b5 b4 b3 b2 b1 b0
OPST STOP — — CMD[3:0]
Value after reset:
00000000
Bit Symbol Bit Name Description R/W
b3 to b0 CMD[3:0] Software Command Setting
b3 b0
0 0 0 1: Program
0 0 1 1: Blank check
0 1 0 0: Block erase
0 1 1 0: All-block erase
Settings other than above are prohibited.*
1
R/W
b5, b4 — Reserved These bits are read as 0. The write value should be 0. R/W
b6 STOP Forced Processing Stop When this bit is set to 1, the processing being executed can be
forcibly stopped.
R/W
b7 OPST Processing Start 0: Processing stops.
1: Processing starts.
R/W
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