R01UH0823EJ0100 Rev.1.00 Page 315 of 1823
Jul 31, 2019
RX23W Group 16. Buses
16.4 Bus Error Monitoring Section
The bus error monitoring section monitors the individual areas for bus errors, and when a bus error occurs, the error is
indicated to the bus master.
16.4.1 Types of Bus Error
There are two types of bus error: illegal address access and timeout.
Illegal address access is the detection of illegal access to an area, and time-out is the detection of a bus-access operation
not being completed within 768 cycles.
16.4.1.1 Illegal Address Access
When the illegal address access detection enable bit (IGAEN) in the bus error monitoring enable register (BEREN) is set
to 1, access to the illegal address ranges will lead to illegal address access errors.
The address ranges where access will lead to illegal address access errors are indicated in
Table 16.5.
16.4.1.2 Timeout
When the timeout detection enable bit (TOEN) in the bus error monitoring enable register (BEREN) is set to 1, bus
access that is not completed within 768 cycles leads to a timeout error.
Internal peripheral buses (2 and 3): Bus access is not completed within 768 peripheral module clock (PCLKB)
cycles from the start of the access. In this MCU, a timeout error does not occur.
Once a timeout error occurs, accesses from the bus master are rejected for 256 PCLKB cycles.
Internal peripheral buses (4): Bus access is not completed within 768 peripheral module clock (PCLKA) cycles
from the start of the access.
Once a timeout error occurs, accesses from the bus master are rejected for 256 PCLKA cycles.
Internal peripheral bus (6): Bus access is not completed within 768 FlashIF clock (FCLK) cycles from the start of
the access.
Once a timeout error occurs, accesses from the bus master are rejected for 256 FCLK cycles. In this MCU, a timeout
error does not occur.
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