Renesas RX Series User Manual

R01UH0823EJ0100 Rev.1.00 Page 314 of 1823
Jul 31, 2019
RX23W Group 16. Buses
When the priority order is toggled, a bus has a lower priority when the request of that bus is accepted.
BPGB[1:0] Bits (Internal Peripheral Bus 2 and 3 Priority Control)
These bits specify the priority order for internal peripheral buses 2 and 3.
When the priority order is fixed, internal main bus 2 has priority over internal main bus 1.
When the priority order is toggled, a bus has a lower priority when the request of that bus is accepted.
BPHB[1:0] Bits (Internal Peripheral Bus 4 Priority Control)
These bits specify the priority order for internal peripheral bus 4.
When the priority order is fixed, internal main bus 2 has priority over internal main bus 1.
When the priority order is toggled, a bus has a lower priority when the request of that bus is accepted.
BPFB[1:0] Bits (Internal Peripheral Bus 6 Priority Control)
These bits specify the priority order for internal peripheral bus 6.
When the priority order is fixed, internal main bus 2 has priority over internal main bus 1.
When the priority order is toggled, a bus has a lower priority when the request of that bus is accepted.

Renesas RX Series Specifications

General

Core	RXv1, RXv2, RXv3
Flash Memory	Up to 8 MB
RAM	Up to 1 MB
Operating Voltage	1.62V to 5.5V
Operating Temperature	-40°C to +85°C or +105°C
Package	BGA, LQFP
ADC Resolution	12-bit
DAC Resolution	12-bit
Communication Interfaces	SCI, SPI, I2C, USB, Ethernet, CAN
Architecture	32-bit
Security Features	Memory Protection Unit (MPU)