Renesas RX Series

R01UH0823EJ0100 Rev.1.00 Page 314 of 1823
Jul 31, 2019
RX23W Group 16. Buses
When the priority order is toggled, a bus has a lower priority when the request of that bus is accepted.
BPGB[1:0] Bits (Internal Peripheral Bus 2 and 3 Priority Control)
These bits specify the priority order for internal peripheral buses 2 and 3.
When the priority order is fixed, internal main bus 2 has priority over internal main bus 1.
When the priority order is toggled, a bus has a lower priority when the request of that bus is accepted.
BPHB[1:0] Bits (Internal Peripheral Bus 4 Priority Control)
These bits specify the priority order for internal peripheral bus 4.
When the priority order is fixed, internal main bus 2 has priority over internal main bus 1.
When the priority order is toggled, a bus has a lower priority when the request of that bus is accepted.
BPFB[1:0] Bits (Internal Peripheral Bus 6 Priority Control)
These bits specify the priority order for internal peripheral bus 6.
When the priority order is fixed, internal main bus 2 has priority over internal main bus 1.
When the priority order is toggled, a bus has a lower priority when the request of that bus is accepted.