R01UH0823EJ0100 Rev.1.00 Page 721 of 1823
Jul 31, 2019
RX23W Group 25. 16-Bit Timer Pulse Unit (TPUa)
25.9.12 Conflict between Overflow/Underflow and Counter Clearing
If overflow/underflow and counter clearing occur simultaneously, TPUm.TCNT is cleared with the generation of the
compare match interrupt and an overflow interrupt is generated.
Figure 25.51 shows the operation timing when a TPUm.TGRy compare match is specified as the clearing source and
FFFFh is set in TGRy.
Figure 25.51 Conflict between Overflow and Counter Clearing
FFFFh
Overflow interrupt signal
Compare match interrupt signal
0000h
TCNT input clock
Counter clear signal
TCNT
PCLK
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