Renesas RX Series User Manual

R01UH0823EJ0100 Rev.1.00 Page 826 of 1823
Jul 31, 2019
RX23W Group 30. Watchdog Timer (WDTA)
30.2.4 WDT Reset Control Register (WDTRCR)
There are some restrictions on writing to the WDTRCR register. For details, refer to section 30.3.2, Control over
Writing to the WDTCR and WDTRCR Registers
.
In auto-start mode, the WDTRCR register settings are disabled, and the settings in option function select register 0
(OFS0) are enabled. The bit setting made to the WDTCR register can also be made in the OFS0 register. For details, refer
to
section 30.3.7, Correspondence between Option Function Select Register 0 (OFS0) and WDT Registers.
30.2.5 Option Function Select Register 0 (OFS0)
For details on the OFS0 register, refer to section 30.3.7, Correspondence between Option Function Select
Register 0 (OFS0) and WDT Registers
.
Address(es): 0008 8026h
b7 b6 b5 b4 b3 b2 b1 b0
RSTIR
QS
———————
Value after reset:
10000000
Bit Symbol Bit Name Description R/W
b6 to b0 — Reserved These bits are read as 0 and cannot be modified. R
b7 RSTIRQS Reset Interrupt Request Selection 0: Non-maskable interrupt request output is enabled
1: Reset output is enabled
R/W

Renesas RX Series Specifications

General

Brand	Renesas
Model	RX Series
Category	Microcontrollers
Language	English