R01UH0823EJ0100 Rev.1.00 Page 69 of 1823
Jul 31, 2019
RX23W Group 2. CPU
2. CPU
The RXv2 instruction set architecture (RXv2) has upward compatibility with the RXv1 instruction set architecture
(RXv1).
Adoption of variable-length instruction format
As with RXv1, the RXv2 CPU has short formats for frequently used instructions, facilitating the development of
efficient programs that take up less memory.
Powerful instruction set
The RXv2 supports 109 selected instructions. Moreover, DSP instructions and floating-point operation instructions
are added, thus realizing high-speed arithmetic processing.
Versatile addressing modes
The RXv2 CPU has 11 versatile addressing modes, with register-register operations, register-memory operations,
and bitwise operations included. Data transfer between memory locations is also possible.
2.1 Features
Minimum instruction execution rate: One clock cycle
Address space: 4-Gbyte linear addresses
Register set of the CPU
General purpose: Sixteen 32-bit registers
Control: Ten 32-bit registers
Accumulator: Two 72-bit registers
Variable-length instruction format (lengths from one to eight bytes)
109 instructions/11 addressing modes
Basic instructions: 75
Floating-point operation instructions: 11
DSP instructions: 23
Processor modes
Supervisor mode and user mode
Vector tables
Exception vector table and interrupt vector table
Memory protection unit
Data arrangement
Selectable as little endian or big endian
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