R01UH0823EJ0100 Rev.1.00 Page 1350 of 1823
Jul 31, 2019
RX23W Group 38. Serial Peripheral Interface (RSPIa)
38.2.10 RSPI Clock Delay Register (SPCKD)
SPCKD sets a period from the beginning of SSLAi signal assertion to RSPCK oscillation (RSPCK delay) when the
SPCMDm.SCKDEN bit is 1. Do not change the SPCKD register while both the SPCR.MSTR and SPCR.SPE bits are 1.
SCKDL[2:0] Bits (RSPCK Delay Setting)
The SCKDL[2:0] bits set an RSPCK delay value when the SPCMDm.SCKDEN bit is 1.
When using the RSPI in slave mode, set the SCKDL[2:0] bits to 000b.
Address(es): RSPI0.SPCKD 0008 838Ch
b7 b6 b5 b4 b3 b2 b1 b0
————— SCKDL[2:0]
Value after reset:
00000000
Bit Symbol Bit Name Description R/W
b2 to b0 SCKDL[2:0] RSPCK Delay Setting
b2 b0
0 0 0: 1 RSPCK
0 0 1: 2 RSPCK
0 1 0: 3 RSPCK
0 1 1: 4 RSPCK
1 0 0: 5 RSPCK
1 0 1: 6 RSPCK
1 1 0: 7 RSPCK
1 1 1: 8 RSPCK
R/W
b7 to b3 — Reserved These bits are read as 0. The write value should be 0. R/W
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