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R01UH0823EJ0100 Rev.1.00 Page 945 of 1823

Jul 31, 2019

RX23W Group 32. USB 2.0 Host/Function Module (USBc)

32.3.7 Bulk Transfers (PIPE1 to PIPE5)

The buffer memory usage (single/double buffer setting) can be selected for bulk transfers. The USB provides the

following functions for bulk transfers.

 BRDY interrupt function (PIPECFG.BFRE bit: refer to

section 32.3.3.1, (2) When the SOFCFG.BRDYM Bit =

0 and the PIPECFG.BFRE Bit = 1

 Transaction count function

(PIPEnTRE.TRENB and TRCLR bits and PIPEnTRN register: refer to

section 32.3.4.5, Transaction Counter

(For PIPE1 to PIPE5 in Reading Direction)

 Response PID = NAK function (PIPECFG.SHTNAK bit: refer to section 32.3.4.8, Response PID = NAK

Function

 Auto response mode (PIPEnCTR.ATREPM bit: refer to section 32.3.4.9, Auto Response Mode)

32.3.8 Interrupt Transfers (PIPE6 to PIPE9)

When the function controller is selected, the USB carries out interrupt transfers in accordance with the timing controlled

by the host controller.

When the host controller is selected, the timing of issuing a token can be specified using the interval counter.

32.3.8.1 Interval Counter during Interrupt Transfers When the Host Controller is

Selected

For interrupt transfers, intervals between transactions are set in the PIPEPERI.IITV[2:0] bits. The USB controller issues

interrupt transfer tokens based on the specified intervals.

(1) Counter Initialization

The interval counter is initialized when the MCU is reset or when the PIPEnCTR.ACLRM bit is set to 1. Note that the

PIPEPERI.IITV[2:0] bits are not initialized when the ACLRM bit is used for initialization.

Note that the interval counter is not initialized in the following case.

 USB bus reset or USB suspended

The IITV[2:0] bits are not initialized. Setting 1 to the DVSTCTR0.UACT bit starts counting from the value before

entering the USB bus reset state or USB suspended state.

(2) Operation When Transmission/Reception is Impossible at Token Issuance Timing

The USB cannot issue tokens even at token issuance timing in the following cases. In such a case, the USB attempts

transactions at the subsequent interval.

 When the PID[1:0] bits are set to 00b (NAK) or 1xb (STALL).

 When the buffer memory is full at the token sending timing in the receiving (IN) direction.

 When there is no data to be sent in the buffer memory at the token sending timing in the transmitting (OUT)

direction.

Renesas RX Series User Manual

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