R01UH0823EJ0100 Rev.1.00 Page 836 of 1823
Jul 31, 2019
RX23W Group 31. Independent Watchdog Timer (IWDTa)
31.2 Register Descriptions
31.2.1 IWDT Refresh Register (IWDTRR)
The IWDTRR register refreshes the counter of the IWDT.
The counter of the IWDT is refreshed by writing 00h and then writing FFh to the IWDTRR register (refresh operation)
within the refresh-permitted period.
After the counter has been refreshed, it starts counting down from the value selected by the IWDTTOPS[1:0] bits in
option function select register 0 (OFS0) in auto-start mode. In register start mode, counting down starts from the value
selected by setting the IWDTCR.TOPS[1:0] bits in the first refresh operation after a reset is released.
When 00h is written, the read value is 00h. When a value other than 00h is written, the read value is FFh.
For details of the refresh operation, refer to
section 31.3.3, Refresh Operation.
Address(es): IWDT.IWDTRR 0008 8030h
b7 b6 b5 b4 b3 b2 b1 b0
Value after reset:
11111111
Bit Description R/W
b7 to b0 The counter is refreshed by writing 00h and then writing FFh to this register. R/W
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