R01UH0823EJ0100 Rev.1.00 Page 835 of 1823
Jul 31, 2019
RX23W Group 31. Independent Watchdog Timer (IWDTa)
To use the IWDT, the IWDT-dedicated clock (IWDTCLK) should be supplied so that the IWDT operates even if the
peripheral module clock (PCLK) stops. The bus interface and registers operate with PCLK, and the 14-bit counter and
control circuits operate with IWDTCLK.
Figure 31.1 is a block diagram of the IWDT.
Figure 31.1 IWDT Block Diagram
IWDT control circuit 14-bit counter
IWDTRR: IWDT refresh register
IWDTCR: IWDT control register
IWDTSR: IWDT status register
IWDTRCR: IWDT reset control register
IWDTCSTPR: IWDT count stop control register
IWDT reset output
IWDTCSTPR
Option function select register 0
(OFS0)
IWDTCLK
IWDTCLK/16
IWDTCLK/64
IWDTCLK/32
IWDTCLK/128
IWDTCLK/256
Reset control circuit
Interrupt control circuit
Clock control circuit
Count stop control output
in sleep mode
Clock
frequency
divider
IWDTCLK
Internal peripheral bus
IWDTRCR
IWDTSR
IWDTCR
IWDTRR
Event link controller
Event signal output
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