R01UH0823EJ0100 Rev.1.00 Page 356 of 1823
Jul 31, 2019
RX23W Group 18. DMA Controller (DMACA)
18.2.13 DMA Module Activation Register (DMAST)
DMST Bit (DMAC Operation Enable)
When this bit is set to 1, DMAC activation is enabled for all channels.
When 1 is written to the DMACm.DMCNT.DTE bit (DMA transfer is enabled) of multiple channels and then this bit is
set to 1 (DMAC activation is enabled), the corresponding multiple channels can be placed in the transfer request
acceptable state at the same time.
When the DMST bit is cleared to 0 during DMA transfer, DMA transfer is suspended after completion of the current data
transfer corresponding to a single transfer request. DMA transfer is resumed by setting the DMST bit to 1 again.
[Setting condition]
When 1 is written to this bit
[Clearing condition]
When 0 is written to this bit
Address(es): 0008 2200h
b7 b6 b5 b4 b3 b2 b1 b0
———————DMST
Value after reset:
00000000
Bit Symbol Bit Name Description R/W
b0 DMST DMAC Operation Enable 0: DMAC activation is disabled.
1: DMAC activation is enabled.
R/W
b7 to b1 — Reserved These bits are read as 0. The write value should be 0. R/W
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