R01UH0823EJ0100 Rev.1.00 Page 1013 of 1823
Jul 31, 2019
RX23W Group 33. Serial Communications Interface (SCIg, SCIh)
33.2.28 Status Clear Register (STCR)
33.2.29 Control Field 0 Data Register (CF0DR)
The CF0DR register is an 8-bit readable and writable register that holds a value for comparison with Control Field 0.
Address(es): SCI12.STCR 0008 B328h
b7 b6 b5 b4 b3 b2 b1 b0
— — AEDCL BCDCL
PIBDC
L
CF1MC
L
CF0MC
L
BFDCL
Value after reset:
00000000
Bit Symbol Bit Name Description R/W
b0 BFDCL BFDF Clear Setting this bit to 1 clears the STR.BFDF flag. This bit is read as 0. R/W
b1 CF0MCL CF0MF Clear Setting this bit to 1 clears the STR.CF0MF flag. This bit is read as 0. R/W
b2 CF1MCL CF1MF Clear Setting this bit to 1 clears the STR.CF1MF flag. This bit is read as 0. R/W
b3 PIBDCL PIBDF Clear Setting this bit to 1 clears the STR.PIBDF flag. This bit is read as 0. R/W
b4 BCDCL BCDF Clear Setting this bit to 1 clears the STR.BCDF flag. This bit is read as 0. R/W
b5 AEDCL AEDF Clear Setting this bit to 1 clears the STR.AEDF flag. This bit is read as 0. R/W
b7, b6 — Reserved These bits are read as 0. The write value should be 0. R/W
Address(es): SCI12.CF0DR 0008 B329h
b7 b6 b5 b4 b3 b2 b1 b0
Value after reset:
00000000
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