R01UH0823EJ0100 Rev.1.00 Page 1193 of 1823
Jul 31, 2019
RX23W Group 36. CAN Module (RSCAN)
36.2 Register Descriptions
36.2.1 Bit Configuration Register L (CFGL)
Modify the CFGL register only in channel reset mode or channel halt mode. Set this register in channel reset mode
before making a transition to channel communication mode or channel halt mode. For setting bit timing, see
section
36.9, Initial Settings
.
BRP[9:0] Bits (Prescaler Division Ratio Set)
The CAN Tq clock (fCANTQ) is obtained by the CAN clock source (fCAN) and setting the clock division ratio with the
BRP[9:0] bits and one clock cycle of the CAN Tq clock is 1 Time Quantum (Tq).
Address(es): RSCAN0.CFGL 000A 8300h
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
—————— BRP[9:0]
Value after reset:
0000000000000000
Bit Symbol Bit Name Description R/W
b9 to b0 BRP[9:0] Prescaler Division Ratio Set When these bits are set to P (0 to 1023), the baud rate
prescaler divides fCAN by P + 1.
R/W
b15 to b10 — Reserved These bits are read as 0. The write value should be 0. R/W
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