R01UH0823EJ0100 Rev.1.00 Page 1324 of 1823
Jul 31, 2019
RX23W Group 37. Serial Sound Interface (SSI)
37.3.5 Transmit Operation
Transmission can be controlled either by DMA/DTC transfer or interrupt.
DMAC/DTC control is preferred to reduce the processor load. In transmission using the DMAC/DTC, the processor will
only receive interrupts if there is an underflow or overflow of data or if DMA/DTC transfer has been completed. In
transmission using DMA/DTC transfer, set the number of DMA/DTC transfers to multiples of 2 to write transmit data to
the SSIFTDR register in 64-bit (two stages of FIFO) units.
The alternative method is using the interrupts that this module generates to supply data as required. In transmission using
interrupts, write transmit data in 64-bit units regardless of the data format. If transmit data ends on a 32-bit boundary,
write 00000000h after the last transmit data is written, and complete writing on a 64-bit boundary.
When stopping transmission, stop writing to the SSIFTDR register while 64-bit writing is completed. After writing is
stopped, wait until a transmit underflow occurs before setting the SSICR.TEN bit to 0. During transmit underflow, the
last data input to SSIFTDR register is continuously transmitted until this module enters the idle state. After setting the
TEN bit to 0, continue to supply the clock
*
1
until the SSISR.IIRQ flag becomes 1 (in idle state). If a transmit underflow
error or transmit overflow error occurs during data transmission, transmit data to SSIFTDR register may not be written in
a 64-bit units. In that case, stop writing data, wait until a transmit underflow error occurs, and check the SSISR.TSWNO
flag when the transmit underflow has occurred. When the TSWNO flag is 1, write 00000000h to SSIFTDR register and
wait until an underflow occurs again. Once the TSWNO flag is confirmed to be 0, Set the TEN bit to 0 and continue to
supply the clock
*
1
until the SSISR.IIRQ flag becomes 1 (in idle state).
Figure 37.18 shows transmission flow using the DMA/DTC, and Figure 37.19 shows transmission flow using
interrupts.
Note 1. Input clock from the SSISCK0 pin when SSICR.SCKD bit = 0.
Master clock when SSICR.SCKD bit = 1.
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