To Next Page

To Previous Page

R01UH0823EJ0100 Rev.1.00 Page 1325 of 1823

Jul 31, 2019

RX23W Group 37. Serial Sound Interface (SSI)

(1) Transmission Using the DMAC/DTC

Figure 37.18 Transmission Using the DMAC/DTC

Start

Set the SSIFCR.AUCKE bit to 1 in master

mode.

Set the SSICR register

configuration bits.

Wait for an interrupt.

Error interrupt?

More data to be sent?

Disable transmit operation,

disable an error interrupt,

enable an idle interrupt.

Wait for an idle interrupt

from this module

End

Yes

Transmit underflow occurred?

Yes

Transmit underflow occurred?

Yes

TSWNO = 0?

Write 32-bit 0-data to the SSIFTDR register.

Clear the transmit underflow error interrupt

status flag.

Yes

Enable an error interrupt,

setup and enable the DMAC/DTC,

enable transmit operation.

End of DMA/DTC transfer?

Enable a transmit interrupt,

enable the DMAC/DTC.

Disable of DMA/DTC transfer

Note 1. When restarting transmission after transmit operation is disabled (TEN = 0) while WS continue mode is

disabled, execute a software reset and go back to the start of the flowchart again.

Note 2. Stop writing transmit data to the SSIFTDR register and wait until a transmit underflow occurs.

During transmit underflow, the last data input to SSIFTDR register is continuously transmitted until the module is

in the idle state.

Renesas RX Series User Manual

Questions and Answers: