R01UH0823EJ0100 Rev.1.00 Page 1020 of 1823
Jul 31, 2019
RX23W Group 33. Serial Communications Interface (SCIg, SCIh)
33.3.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode
In asynchronous mode, the SCI operates on a base clock with a frequency of 16 times*
1
the bit rate.
In reception, the SCI samples the falling edge of the start bit using the base clock, and performs internal synchronization.
Since receive data is sampled at the rising edge of the 8th pulse
*
1
of the base clock, data is latched at the middle of each
bit, as shown in
Figure 33.6. Thus the reception margin in asynchronous mode is determined by formula (1) below.
(%) ··· Formula (1)
M: Reception margin
N: Ratio of bit rate to clock
(N = 16 when SEMR.ABCS = 0, N = 8 when SEMR.ABCS = 1)
D: Duty cycle of clock (D = 0.5 to 1.0)
L: Frame length (L = 9 to 13)
F: Absolute value of clock frequency deviation
Assuming values of F = 0 and D = 0.5 in formula (1), the reception margin is determined by the formula below.
M = {0.5 – 1/(2 × 16)} × 100 (%) = 46.875 (%)
However, this is only the computed value, and a margin of 20% to 30% should be allowed in system design.
Note 1. This is an example when the ABCS bit in the SEMR register is 0. When the ABCS bit is 1, a frequency of 8 times
the bit rate is used as a base clock and receive data is sampled at the rising edge of the 4th pulse of the base
clock.
Figure 33.6 Receive Data Sampling Timing in Asynchronous Mode
M0.5
1
2N
--------–
L0.5–F–
D0.5–
N
---------------------
1F+– 100=
Receive data (RXDn)
Base clock
D0 D1
Synchronization
sampling timing
Data sampling
timing
Start bit
8 clock pulses
16 clock pulses
015701570
To Next Page
Loading...
Need help?
General
