Renesas RX Series User Manual

R01UH0823EJ0100 Rev.1.00 Page 1557 of 1823
Jul 31, 2019
RX23W Group 44. 12-Bit A/D Converter (S12ADE)
44.2.16 A/D Event Link Control Register (ADELCCR)
x: Don't care
ADELCCR sets the generation conditions of the ELC scan end event (S12ADELC).
ELCC[1:0] Bits (Event Link Control)
These bits select the generation conditions of the scan end event (S12ADELC) for the ELC.
Address(es): S12AD.ADELCCR 0008 907Dh
b7 b6 b5 b4 b3 b2 b1 b0
——————ELCC[1:0]
Value after reset:
00000000
Bit Symbol Bit Name Description R/W
b1, b0 ELCC[1:0] Event Link Control
b1 b0
0 0: Event is generated on completion of the scan other than group
B in group scan mode
0 1: Event is generated on completion of the scan of group B in
group scan mode
1 x: Event is generated on completion of all scans
R/W
b7 to b2 — Reserved These bits are read as 0. The write value should be 0. R/W

Renesas RX Series Specifications

General

Core	RXv1, RXv2, RXv3
Flash Memory	Up to 8 MB
RAM	Up to 1 MB
Operating Voltage	1.62V to 5.5V
Operating Temperature	-40°C to +85°C or +105°C
Package	BGA, LQFP
ADC Resolution	12-bit
DAC Resolution	12-bit
Communication Interfaces	SCI, SPI, I2C, USB, Ethernet, CAN
Architecture	32-bit
Security Features	Memory Protection Unit (MPU)