Renesas RX Series - Timer Interrupt Enable Register (TIER)

R01UH0823EJ0100 Rev.1.00 Page 491 of 1823
Jul 31, 2019
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a)
23.2.4 Timer Interrupt Enable Register (TIER)
 MTU0.TIER, MTU3.TIER
 MTU1.TIER, MTU2.TIER
 MTU4.TIER
The MTU has a total of six TIER registers, two each for MTU0 and one each for MTU1 to MTU4.
The TIER register enables or disables interrupt requests in each channel.
Address(es): MTU0.TIER 000D 0B04h, MTU3.TIER 000D 0A08h
b7 b6 b5 b4 b3 b2 b1 b0
TTGE — — TCIEV TGIED TGIEC TGIEB TGIEA
Value after reset:
00000000
Address(es): MTU1.TIER 000D 0B84h, MTU2.TIER 000D 0C04h
b7 b6 b5 b4 b3 b2 b1 b0
TTGE — TCIEU TCIEV — — TGIEB TGIEA
Value after reset:
00000000
Address(es): MTU4.TIER 000D 0A09h
b7 b6 b5 b4 b3 b2 b1 b0
TTGE TTGE2 — TCIEV TGIED TGIEC TGIEB TGIEA
Value after reset:
00000000
Bit Symbol Bit Name Description R/W
b0 TGIEA TGR Interrupt Enable A 0: Interrupt requests (TGIA) disabled
1: Interrupt requests (TGIA) enabled
R/W
b1 TGIEB TGR Interrupt Enable B 0: Interrupt requests (TGIB) disabled
1: Interrupt requests (TGIB) enabled
R/W
b2 TGIEC TGR Interrupt Enable C 0: Interrupt requests (TGIC) disabled
1: Interrupt requests (TGIC) enabled
R/W
b3 TGIED TGR Interrupt Enable D 0: Interrupt requests (TGID) disabled
1: Interrupt requests (TGID) enabled
R/W
b4 TCIEV Overflow Interrupt Enable 0: Interrupt requests (TCIV) disabled
1: Interrupt requests (TCIV) enabled
R/W
b5 TCIEU Underflow Interrupt Enable 0: Interrupt requests (TCIU) disabled
1: Interrupt requests (TCIU) enabled
R/W
b6 TTGE2 A/D Converter Start Request Enable 2 0: A/D converter start request generation by MTU4.TCNT
underflow (trough) disabled
1: A/D converter start request generation by MTU4.TCNT
underflow (trough) enabled
R/W
b7 TTGE A/D Converter Start Request Enable 0: A/D converter start request generation disabled
1: A/D converter start request generation enabled
R/W