R01UH0823EJ0100 Rev.1.00 Page 492 of 1823
Jul 31, 2019
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a)
TGIEA and TGIEB Bits (TGR Interrupt Enable A and B)
Each bit enables or disables interrupt requests (TGIm) (m = A, B).
TGIEC and TGIED Bits (TGR Interrupt Enable C and D)
Each bit enables or disables interrupt requests (TGIm) in MTU0, MTU3, and MTU4 (m = C, D).
In MTU1 and MTU2, these bits are reserved. They are read as 0. The write value should be 0.
TCIEV Bit (Overflow Interrupt Enable)
This bit enables or disables interrupt requests (TCIV).
TCIEU Bit (Underflow Interrupt Enable)
This bit enables or disables interrupt requests (TCIU) in MTU1 and MTU2.
In MTU0, MTU3, and MTU4, this bit is reserved. It is read as 0. The write value should be 0.
TTGE2 Bit (A/D Converter Start Request Enable 2)
This bit enables or disables generation of A/D converter start requests by MTU4.TCNT underflow (trough) in
complementary PWM mode.
In MTU0 to MTU3, this bit is reserved. It is read as 0. The write value should be 0.
TTGE Bit (A/D Converter Start Request Enable)
This bit enables or disables generation of A/D converter start requests by the TGRA input capture/compare match.
MTU0.TIER2
TGIEE and TGIEF Bits (TGR Interrupt Enable E and F)
Each bit enables or disables interrupt requests by compare match between the MTU0.TCNT counter and the
MTU0.TGRm register (m = E, F).
Address(es): MTU0.TIER2 000D 0B24h
b7 b6 b5 b4 b3 b2 b1 b0
——————TGIEFTGIEE
Value after reset:
00000000
Bit Symbol Bit Name Description R/W
b0 TGIEE TGR Interrupt Enable E 0: Interrupt requests (TGIE) disabled
1: Interrupt requests (TGIE) enabled
R/W
b1 TGIEF TGR Interrupt Enable F 0: Interrupt requests (TGIF) disabled
1: Interrupt requests (TGIF) enabled
R/W
b7 to b2 — Reserved These bits are read as 0. The write value should be 0. R/W
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