R01UH0823EJ0100 Rev.1.00 Page 638 of 1823
Jul 31, 2019
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a)
23.8 Operations Linked by the ELC
23.8.1 Event Signal Output to the ELC
The MTU is capable of operation linked with another module set in advance when its interrupt request signal is used as
an event signal by the event link controller (ELC).
The MTU outputs the event signal regardless of the setting of the corresponding interrupt request enable bit.
23.8.2 MTU Operations in Response to Receiving Event Signals from the ELC
The MTU can perform the following operations in response to the event set in advance in the ELSRn register of the event
link controller (ELC).
(1) Count Start Operation
The MTU is selected the count start operation when using the ELOPA and ELOPB registers setting of the ELC. The
ELOPA register functions to MTU1 to MTU3, and ELOPB register functions to MTU4. The TMDR register of the
channel set by MTU should be set to the value after reset, 00h. When the specified event is generated by the ELSRn
register, the TSTR.CSTn bit shown in
Table 23.57 is set to 1, then the MTU counter is started.
However, when the specified event is generated while the TSTR.CSTn bit is set to 1, the event is disabled.
Table 23.57
lists the TSTR register bits used for each channel.
For details on the count start operation setting, refer to
section 23.3.1, (1) Counter Operation.
(2) Input Capture Operation
The MTU is selected the input capture operation when using the ELOPA and ELOPB registers setting of the ELC. The
ELOPA register handles MTU1 to MTU3, and ELOPB register handles MTU4. The TMDR register of the channel set by
MTU should be set to the value after reset, 00h. When the specified event is generated by the ELSRn register, then the
TCNT counter value capture to TGR register. When using the input capture operation, after setting the bit of the TIOR
register to the input capture, the TSTR.CSTn bit should be set to 1, and start the counter.
Then, the TIOCnA pin (input capture pin) input is disabled.
Table 23.58 lists the timer general register and timer I/O control register used in the input capture operation by the ELC.
For details on the input capture setting, refer to
section 23.3.1, (3) Input Capture Function.
Table 23.57 Linkage Operating TSTR Register by the ELC
Channel No. TSTR Register
MTU1 TSTR.CST1 bit
MTU2 TSTR.CST2 bit
MTU3 TSTR.CST3 bit
MTU4 TSTR.CST4 bit
Table 23.58 Timer General Register and Timer I/O Control Register Used in the Input Capture Operation
by the ELC
Channel No. Register Name Bit Name of TIOR Register
MTU1 MTU1.TGRA register MTU1.TIOR.IOA[3:0] bits
MTU2 MTU2.TGRA register MTU2.TIOR.IOA[3:0] bits
MTU3 MTU3.TGRA register MTU3.TIORH.IOA[3:0] bits
MTU4 MTU4.TGRA register MTU4.TIORH.IOA[3:0] bits
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