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R01UH0823EJ0100 Rev.1.00 Page 1351 of 1823

Jul 31, 2019

RX23W Group 38. Serial Peripheral Interface (RSPIa)

38.2.11 RSPI Slave Select Negation Delay Register (SSLND)

SSLND sets a period (SSL negation delay) from the transmission of a final RSPCK edge to the negation of the SSLAi

signal during a serial transfer by the RSPI in master mode. Do not change the SSLND register while both the

SPCR.MSTR and SPCR.SPE bits are 1.

SLNDL[2:0] Bits (SSL Negation Delay Setting)

The SLNDL[2:0] bits set an SSL negation delay value when the RSPI is in master mode.

When using the RSPI in slave mode, set the SLNDL[2:0] bits to 000b.

Address(es): RSPI0.SSLND 0008 838Dh

b7 b6 b5 b4 b3 b2 b1 b0

————— SLNDL[2:0]

Value after reset:

00000000

Bit Symbol Bit Name Description R/W

b2 to b0 SLNDL[2:0] SSL Negation Delay Setting

b2 b0

0 0 0: 1 RSPCK

0 0 1: 2 RSPCK

0 1 0: 3 RSPCK

0 1 1: 4 RSPCK

1 0 0: 5 RSPCK

1 0 1: 6 RSPCK

1 1 0: 7 RSPCK

1 1 1: 8 RSPCK

R/W

b7 to b3 — Reserved These bits are read as 0. The write value should be 0. R/W

Renesas RX Series User Manual

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