R01UH0823EJ0100 Rev.1.00 Page 398 of 1823
Jul 31, 2019
RX23W Group 19. Data Transfer Controller (DTCa)
19.4.6 Chain Transfer
Setting the MRB.CHNE bit to 1 allows chain transfer to be performed continuously on a single transfer request.
If the MRB.CHNE bit is 1 and the MRB.CHNS bit is 0, an interrupt request to the CPU is not generated when the
specified number of data transfers is completed, or while the MRB.DISEL bit is 1 (an interrupt request to the CPU is
generated for every data transfer). Data transfer has no effect on the interrupt status flag, which is the request source.
The transfer information (SAR, DAR, CRA, CRB, MRA, and MRB) that define a data transfer can be specified
independently of each other.
Figure 19.8 shows chain transfer operation.
Figure 19.8 Chain Transfer Operation
If the MRB.CHNE bit is 1 and the CHNS bit is 1, chain transfer is performed only after completion of specified number
of data transfers. In repeat transfer mode, chain transfer is performed after completion of specified number of data
transfers.
For details on chain transfer conditions, refer to
Table 19.3, Chain Transfer Conditions.
Transfer information
CHNE bit = 1
Transfer information
allocated in the RAM
Data area
Transfer source data (1)
Start address of transfer
information
DTC vector table
DTC vector
address
Transfer information
CHNE bit = 0
Transfer destination data (1)
Transfer source data (2)
Transfer destination data (2)
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