R01UH0823EJ0100 Rev.1.00 Page 731 of 1823
Jul 31, 2019
RX23W Group 26. 8-Bit Timer (TMR)
26.2 Register Descriptions
26.2.1 Timer Counter (TCNT)
TCNT is an 8-bit readable/writable up-counter.
TMR0.TCNT and TMR1.TCNT (TMR2.TCNT and TMR3.TCNT) comprise a single 16-bit counter (TMR01.TCNT,
TMR23.TCNT) so they can be accessed together by a word transfer instruction.
The TCCR.CSS[1:0] and CKS[2:0] bits are used to select a count clock.
TCNT can be cleared by an external counter reset signal, compare match A, or compare match B. Which compare match
to be used for clearing is selected by the TCR.CCLR[1:0] bits.
When TCNT overflows (its value changes from FFh to 00h), an overflow interrupt (low-level pulse) is output provided
the interrupt request is enabled by the TCR.OVIE bit.
For details on the corresponding interrupt vector number, refer to
section 15, Interrupt Controller (ICUb), and Tab le
26.6, TMR Interrupt Sources
.
Table 26.4 Register Allocation for 16-Bit Access
Address Register Upper 8 Bits Lower 8 Bits
0008 8208h TMR01.TCNT TMR0.TCNT TMR1.TCNT
0008 8204h TMR01.TCORA TMR0.TCORA TMR1.TCORA
0008 8206h TMR01.TCORB TMR0.TCORB TMR1.TCORB
0008 820Ah TMR01.TCCR TMR0.TCCR TMR1.TCCR
0008 8218h TMR23.TCNT TMR2.TCNT TMR3.TCNT
0008 8214h TMR23.TCORA TMR2.TCORA TMR3.TCORA
0008 8216h TMR23.TCORB TMR2.TCORB TMR3.TCORB
0008 821Ah TMR23.TCCR TMR2.TCCR TMR3.TCCR
Address(es): TMR0.TCNT 0008 8208h, TMR1.TCNT 0008 8209h, TMR2.TCNT 0008 8218h, TMR3.TCNT 0008 8219h,
TMR01.TCNT 0008 8208h, TMR23.TCNT 0008 8218h
TMR01.TCNT (TMR23.TCNT)
TMR0.TCNT (TMR2.TCNT) TMR1.TCNT (TMR3.TCNT)
b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0
Value after reset:
0000000000000000
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