R01UH0823EJ0100 Rev.1.00 Page 353 of 1823
Jul 31, 2019
RX23W Group 18. DMA Controller (DMACA)
18.2.11 DMA Status Register (DMSTS)
Note 1. Only 0 can be written to clear the flag.
ESIF Flag (Transfer Escape End Interrupt Flag)
This flag indicates that the transfer escape end interrupt has been generated.
[Setting conditions]
When 1-repeat size data transfer is completed in repeat transfer mode with the RPTIE bit in DMINT set to 1.
When 1-block data transfer is completed in block transfer mode with the RPTIE bit in DMINT set to 1.
When an extended repeat area overflow on the source address occurs while the SARIE bit in DMINT is set to 1 and
the SARA[4:0] bits in DMAMD are set to a value other than 00000b (extended repeat area is specified on the
transfer source address)
When an extended repeat area overflow on the destination address occurs while the DARIE bit in DMINT is set to 1
and the DARA[4:0] bits in DMAMD are set to a value other than 00000b (extended repeat area is specified on the
transfer destination address)
[Clearing conditions]
When 0 is written to this bit.
When 1 is written to the DTE bit in DMCNT.
Address(es): DMAC0.DMSTS 0008 201Eh, DMAC1.DMSTS 0008 205Eh, DMAC2.DMSTS 0008 209Eh, DMAC3.DMSTS 0008 20DEh
b7 b6 b5 b4 b3 b2 b1 b0
ACT — — DTIF — — — ESIF
Value after reset:
00000000
Bit Symbol Bit Name Description R/W
b0 ESIF Transfer Escape End Interrupt
Flag
0: A transfer escape end interrupt has not been generated.
1: A transfer escape end interrupt has been generated.
R/W*
1
b3 to b1 — Reserved These bits are read as 0. Writing to these bits has no effect. R
b4 DTIF Transfer End Interrupt Flag 0: A transfer end interrupt has not been generated.
1: A transfer end interrupt has been generated.
R/W*
1
b6, b5 — Reserved These bits are read as 0. Writing to these bits has no effect. R
b7 ACT DMA Active Flag 0: DMAC operation is suspended.
1: DMAC is operating.
R
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