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Renesas RX Series User Manual

Renesas RX Series
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R01UH0823EJ0100 Rev.1.00 Page 939 of 1823
Jul 31, 2019
RX23W Group 32. USB 2.0 Host/Function Module (USBc)
32.3.4.11 Null Auto Response Mode
With the pipes for bulk IN transfer, zero-length packets are continuously transmitted when the PIPEnCTR.ATREPM bit
is set to 1.
To make a transition from normal mode to null auto response mode, null auto response mode should be set in the pipe
operation disabled state (response PID = NAK) before enabling pipe operation (response PID = BUF). After pipe
operation has been enabled, null auto response mode becomes valid. Before setting null auto response mode, the
PIPEnCTR.INBUFM = 0 should be confirmed because the mode can be set only when the buffer is empty. If the
INBUFM flag is 1, the buffer should be emptied with the PIPEnCTR.ACLRM bit. While a transition to null auto
response mode is being made, data should not be written from the FIFO port.
To make a transition from null auto response mode to normal mode, pipe operation disabled state (response PID = NAK)
should be retained for the period of zero-length packet transmission (about 10 µs) before canceling null auto response
mode. In normal mode, data can be written from the FIFO port; therefore, packet transmission to the host is enabled by
enabling pipe operation (response PID = BUF).
32.3.5 FIFO Buffer Memory
32.3.5.1 FIFO Buffer Memory
The USB has FIFO buffer memory for data transfer. The memory area used for each pipe is managed by the USB. The
FIFO buffer memory has two states depending on whether the access right is assigned to the system (CPU side) or the
USB (SIE side).
(1) Buffer Status
Table 32.16 and Table 32.17 show the buffer status in the USB. The buffer memory status can be confirmed using the
DCPCTR.BSTS flag and the PIPEnCTR.INBUFM flag. The transfer direction for the buffer memory can be specified
using either the PIPECFG.DIR bit or the CFIFOSEL.ISEL bit (when DCP is selected).
The INBUFM flag is valid for PIPE0 to PIPE5 in the transmitting direction.
When a transmitting pipe uses the double buffer configuration, software can read the BSTS flag to monitor the buffer
memory status on the CPU side and the INBUFM flag to monitor the buffer memory status on the SIE side. When the
BEMP interrupt may not show the buffer empty status because the write access to the FIFO port by the CPU or DMAC/
DTC is slow, software can use the INBUFM flag to confirm the end of transmission.
Table 32.16 Buffer Status Indicated by the BSTS Flag
ISEL or DIR BSTS Buffer Memory Status
0 (receiving direction) 0 There is no received data, or data is being received.
Reading from the FIFO port is disabled.
0 (receiving direction) 1 There is received data, or a zero-length packet has been received.
Reading from the FIFO port is allowed.
Note that when a zero-length packet is received, reading is not possible and the buffer must be
cleared.
1 (transmitting direction) 0 The transmission has not been completed.
Writing to the FIFO port is disabled.
1 (transmitting direction) 1 The transmission has been completed.
CPU write is allowed.

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Renesas RX Series Specifications

General IconGeneral
CoreRXv1, RXv2, RXv3
Flash MemoryUp to 8 MB
RAMUp to 1 MB
Operating Voltage1.62V to 5.5V
Operating Temperature-40°C to +85°C or +105°C
PackageBGA, LQFP
ADC Resolution12-bit
DAC Resolution12-bit
Communication InterfacesSCI, SPI, I2C, USB, Ethernet, CAN
Architecture32-bit
Security FeaturesMemory Protection Unit (MPU)

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