Renesas RX Series - DMA Controller (DMACA); Overview

R01UH0823EJ0100 Rev.1.00 Page 338 of 1823
Jul 31, 2019
RX23W Group 18. DMA Controller (DMACA)
18. DMA Controller (DMACA)
This MCU incorporates a 4-channel direct memory access controller (DMAC).
The DMAC module performs data transfers without the CPU. When a DMA transfer request is generated, the DMAC
transfers data stored at the transfer source address to the transfer destination address.
18.1 Overview
Table 18.1 lists the specifications of the DMAC, and Figure 18.1 shows a block diagram of the DMAC.
Note 1. For details on DMAC activation sources, see Table 15.3, Interrupt Vector Table in section 15, Interrupt Controller (ICUb).
Table 18.1 Specifications of DMAC
Item Description
Number of channels 4 (DMACm (m = 0 to 3))
Transfer space 512 Mbytes
(0000 0000h to 0FFF FFFFh and F000 0000h to FFFF FFFFh excluding reserved areas)
Maximum transfer volume 1M data
(Maximum number of transfers in block transfer mode: 1,024 data × 1,024 blocks)
DMA request source
 Activation source selectable for each channel
Software trigger
Interrupt requests from peripheral modules or trigger input to external interrupt input pins*
1
Channel priority Channel 0 > Channel 1 > Channel 2 > Channel 3 (Channel 0: Highest)
Transfer
data
Single data Bit length: 8, 16, 32 bits
Block size Number of data: 1 to 1,024
Transfer
mode
Normal transfer mode
 One data transfer by one DMA transfer request
 Free running mode (setting in which total number of data transfers is not specified) settable
Repeat transfer mode
 One data transfer by one DMA transfer request
 Program returns to the transfer start address on completion of the repeat size of data
transfer specified for the transfer source or destination.
 Maximum settable repeat size: 1,024
Block transfer mode
 One block data transfer by one DMA transfer request
 Maximum settable block size: 1,024 data
Selective
functions
Extended repeat area
function
 Function in which data can be transferred by repeating the address values in the specified
range with the upper bit values in the transfer address register fixed
 Area of 2 bytes to 128 Mbytes separately settable as extended repeat area for transfer
source and destination
Interrupt
request
Transfer end interrupt Generated on completion of transferring data volume specified by the transfer counter.
Transfer escape end
interrupt
Generated when the repeat size of data transfer is completed or the extended repeat area
overflows.
Power consumption reduction function Module stop state can be set.
Event link function Event link request is generated after one data transfer (for block, after one block transfer).