R01UH0823EJ0100 Rev.1.00 Page 1087 of 1823
Jul 31, 2019
RX23W Group 33. Serial Communications Interface (SCIg, SCIh)
33.10.5 Digital Filter for Input on the RXDX12 Pin
Signals input through the RXDX12 pin can be passed through a digital filter before they are conveyed to the internal
circuits. The digital filter consists of three flip-flop circuit stages connected in series and a match-detecting circuit. The
CR2.DFCS[2:0] bits select the sampling clock for the RXDX12 pin input signals. If the outputs of all three latches
match, the given level is conveyed to subsequent circuits. If the levels do not match, the previous value is retained. In
other words, levels are confirmed as being the signal if they are retained for at least three cycles of the sampling clock but
judged to be noise rather than changes in the signal level if they change within three cycles of the sampling clock.
Figure
33.70
shows an example of operations with the digital filter.
Figure 33.70 Example of Operations with the Digital Filter
Sampling clock
RXDX12 input signal after
passing through the digital filter
Clock period selected by
DFCS[2:0]
Change in signal level is not recognized
due to not matching 3 times.
Delay in signal propagation:
up to 3 sampling-clock cycles
D
C
Q
Match-
detection
circuit
RXDX12 input
signal
PCLK/8
PCLK/16
PCLK/32
PCLK/64
PCLK/128
Sampling clock
Base clock
CR2.DFCS[2:0]
D
C
QD
C
Q
RXDX12 input signal
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