Renesas RX Series User Manual

R01UH0823EJ0100 Rev.1.00 Page 1366 of 1823
Jul 31, 2019
RX23W Group 38. Serial Peripheral Interface (RSPIa)
38.3.4 Data Format
The RSPI’s data format depends on the settings in RSPI command register m (SPCMDm) (m = 0 to 7) and the parity
enable bit in RSPI control register 2 (SPCR2.SPPE). Regardless of whether the MSB or LSB is first, the RSPI treats the
range from the LSB bit in the RSPI data register (SPDR) to the selected data length as transfer data.
The format of one frame of data before or after transfer is shown below.
(a) With Parity Disabled
When parity is disabled, transmission or reception of data proceeds with the length in bits selected in the RSPI data
length setting bits in RSPI command register m (SPCMDm.SPB[3:0]).
(b) With Parity Enabled
When parity is enabled, transmission or reception of data proceeds with the length in bits selected in the RSPI data length
setting bits in RSPI command register m (SPCMDm.SPB[3:0]). In this case, however, the last bit is a parity bit.
Figure 38.13 Outline of the Data Format (with Parity Disabled/Enabled)
D0 D1 D2 Dn-2 Dn-1 P
SPCMDm.SPB[3:0] (m = SPSSR.SPCP[2:0])
With parity enabled
D0 D1 D2 Dn-2 Dn-1 Dn
SPCMDm.SPB[3:0] (m = SPSSR.SPCP[2:0])
With parity disabled

Renesas RX Series Specifications

General

Core	RXv1, RXv2, RXv3
Flash Memory	Up to 8 MB
RAM	Up to 1 MB
Operating Voltage	1.62V to 5.5V
Operating Temperature	-40°C to +85°C or +105°C
Package	BGA, LQFP
ADC Resolution	12-bit
DAC Resolution	12-bit
Communication Interfaces	SCI, SPI, I2C, USB, Ethernet, CAN
Architecture	32-bit
Security Features	Memory Protection Unit (MPU)