Renesas RX Series

R01UH0823EJ0100 Rev.1.00 Page 1310 of 1823
Jul 31, 2019
RX23W Group 37. Serial Sound Interface (SSI)
confirming it to be 1.
If TUIRQ flag = 1 and SSICR.TUIEN bit = 1, an interrupt occurs.
If TUIRQ flag = 1, the SSIFTDR register did not have data written to it before it was required for transmission. This may
lead to the same data being transmitted once more.
Note: When a transmit underflow occurs, the last data input to the SSIFTDR register is transmitted until this module is
in the idle state after transmission is stopped.
37.2.3 FIFO Control Register (SSIFCR)
Note 1. The RXI request can be cleared by setting the SSIFSR.RDF flag to 0 (see the description of the SSIFSR.RDF flag for details) or
RIE bit to 0.
Note 2. The TXI request can be cleared by setting the SSIFSR.TDE flag to 0 (see the description of the SSIFSR.TDE flag for details) or
TIE bit to 0.
Note 3. The values in parenthesis are the number of empty stages in SSIFTDR at which the SSIFSR.TDE flag is set.
Note 4. Rewriting is allowed only in the idle state.
The SSIFCR register resets the number of the data bytes stored in the SSIFTDR and SSIFRDR registers, and specifies
transmit FIFO and receive FIFO threshold values.
Address(es): SSI0.SSIFCR 0008 A510h
b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16
AUCKE——————————————
SSIRS
T
Value after reset:
0000000000000000
b15b14b13b12b11b10b9b8b7b6b5b4b3b2b1b0
————————TTRG[1:0] RTRG[1:0]TIERIETFRSTRFRST
Value after reset:
0000000000000000
Bit Symbol Bit Name Description R/W
b0 RFRST Receive FIFO Data Register
Reset*
4
0: Release the receive FIFO data reset.
1: Initiates the receive FIFO data reset.
R/W
b1 TFRST Transmit FIFO Data Register
Reset*
4
0: Release the transmit FIFO data reset.
1: Initiates the transmit FIFO data reset.
R/W
b2 RIE Receive Data Full Interrupt
Enable
0: Receive data full interrupt (RXI) request is disabled.
1: Receive data full interrupt (RXI) request is enabled.*
1
R/W
b3 TIE Transmit Data Empty Interrupt
Enable
0: Transmit data empty interrupt (TXI) request is disabled.
1: Transmit data empty interrupt (TXI) request is enabled.*
2
R/W
b5, b4 RTRG[1:0] Receive FIFO Threshold Setting
*
4
b5 b4
00:1
01:2
10:4
11:6
R/W
b7, b6 TTRG[1:0] Transmit FIFO Threshold Setting
*
4
b7 b6
00:7 (1)*
3
01:6 (2)*
3
10:4 (4)*
3
11:2 (6)*
3
R/W
b15 to b8 — Reserved These bits are read as undefined. The write value should be 0. R/W
b16 SSIRST SSI Software Reset 0: Clears the SSI software reset.
1: Initiates the SSI software reset.
R/W
b30 to b17 — Reserved These bits are read as undefined. The write value should be 0. R/W
b31 AUCKE Master Clock Enable*
4
0: The master clock is disabled.
1: The master clock is enabled.
R/W