Renesas RX Series User Manual

R01UH0823EJ0100 Rev.1.00 Page 1342 of 1823
Jul 31, 2019
RX23W Group 38. Serial Peripheral Interface (RSPIa)
38.2.5 RSPI Data Register (SPDR)
 When accessing in longword size
 When accessing in word size
SPDR is the interface with the buffers that hold data for transmission and reception by the RSPI.
When accessing in longwords (the SPLW bit is 1), access SPDR in 32-bit units.
When accessing in words (the SPLW bit is 0), access SPDR.H in 16-bit units.
The transmit buffer (SPTX) and receive buffer (SPRX) are independent but are both mapped to SPDR.
Figure 38.2
shows the Configuration of SPDR.
Figure 38.2 Configuration of SPDR
The transmit and receive buffers each have four stages. The number of stages to be used is selectable by the number of
frames specification bits in the RSPI data control register (SPDCR.SPFC[1:0]). The eight stages of the buffer are all
Address(es): RSPI0.SPDR 0008 8384h
b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16
Value after reset:
0000000000000000
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
Value after reset:
0000000000000000
Address(es): RSPI0.SPDR.H 0008 8384h
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
H
Value after reset:
0000000000000000
SPTX0
SPTX1
SPTX2
SPTX3
SPRX0
SPRX1
SPRX2
SPRX3
Internal peripheral bus
Transmit buffer
SPDR
Shift
register
Receive buffer
Transmit data
Receive data
*1
RSPI data register
*1
*1
*1
Note 1. The destination buffer and stage for access is automatically switched by hardware.
Shift
register

Renesas RX Series Specifications

General

Brand	Renesas
Model	RX Series
Category	Microcontrollers
Language	English