Renesas RX Series User Manual

R01UH0823EJ0100 Rev.1.00 Page 1069 of 1823
Jul 31, 2019
RX23W Group 33. Serial Communications Interface (SCIg, SCIh)
33.7.6 Master Reception (Simple I
2
C Mode)
Figure 33.55 shows an example of operations in simple I
2
C mode master reception and Figure 33.56 is a flowchart
showing the procedure for master reception.
The value of the SIMR2.IICINTM bit is assumed to be 1 (use reception and transmission interrupts).
In simple I
2
C mode, the transmit data empty interrupt (TXI) is generated when communication of one frame is
completed, unlike the TXI interrupt request generation timing during clock synchronous transmission.
Figure 33.55 Example of Operations for Master Reception in Simple I
2
C-bus Mode
(with 7-Bit Slave Addresses, Transmission Interrupts, and Reception Interrupts in Use)
TXI interrupt flag
(IRn in the ICU
*
1
)
SSDAn
SSCLn
Generation of STI interrupt request
STI interrupt flag
(IRn in the ICU
*
1
)
Acceptance of STI interrupt request
Generation of TXI interrupt request
Acceptance of TXI interrupt request
Generation of TXI interrupt request
Generation of STI interrupt request
D7 D6 D1 D0
ACK
D7 D6 D1 D0
NACK
Slave address (7 bits)
R
Received data
Start
condition
Stop condition
RXI interrupt flag
(IRn in the ICU
*
1
)
Generation of RXI interrupt request
RXI is assumed to have been disabled by
setting SCR.RIE = 0.
Note1. Refer to section 15, Interrupt Controller (ICUb) for details on the corresponding interrupt vector number.

Renesas RX Series Specifications

General

Brand	Renesas
Model	RX Series
Category	Microcontrollers
Language	English