End
Initialization
Start of transmission
[ 1 ]
No
Yes
STI interrupt?
[ 2 ]
Simultaneously set the SIMR3.IICSTAREQ
bit to 1 and the SIMR3.IICSCLS[1:0] and
IICSDAS[1:0] bits to 01b
Set the SIMR3.IICSTIF to 0, and set the
SIMR3.IICSCLS[1:0] and IICSDAS[1:0] bits to
00b
Write the slave address and value for the
R/W bit in TDR
No
Yes
No
Yes
SISR.IICACKR = 0?
[ 3 ]
Write transmit data in TDR
No
Yes
TXI interrupt?
No
Yes
All data transmitted?
No
Yes
STI interrupt?
Simultaneously set the SIMR3.IICSTPREQ
bit to 1 and the SIMR3.IICSCLS[1:0] and
IICSDAS[1:0] bits to 01b
Set the SIMR3.IICSTIF to 0, and set the
SIMR3.IICSCLS[1:0] and IICSDAS[1:0] bits to
11b
TXI interrupt?
[ 5 ]
[ 4 ]
If 10-bit slave addresses are in use, processing of [3] and [4]
is repeated twice.
[ 6 ]
[ 1 ] Initialization for simple I
2
C mode
For transmission, set the SCR.RIE bit to 0 (RXI and ERI
interrupts requests are disabled)
[ 2 ] Generate a start condition.
[ 3 ] Writing to TDR:
Writing the slave address and value for the R/W bit to TDR.
[ 4 ] Confirming ACK response from the slave address:
Check the SISR.IICACKR bit. If its value is 0, it is indicated
that the slave device responded with ACK and operations
proceed. If its value is 1, it is indicated that there was no
response from a slave device so the next transition is to
generation of the stop condition.
[ 5 ] Steps for continuing with serial transmission:
When transmission is to continue, write further transmit data
to TDR. Except for the first data to be transmitted, a TXI
request can activate the DMAC or DTC to handle writing of
data to TDR.
[ 6 ] Generation of a stop condition.
Note: In simple I
2
C mode, the TXI interrupt request is generated
when communication is completed, unlike the timing during
clock synchronous transmission.
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