R01UH0823EJ0100 Rev.1.00 Page 1017 of 1823
Jul 31, 2019
RX23W Group 33. Serial Communications Interface (SCIg, SCIh)
33.2.38 Timer Prescaler Register (TPRE)
TPRE consists of an 8-bit reload register, a read buffer, and a counter, each of which has FFh as its initial value. The
counter counts down in synchronization with the counter clock selected by the TMR.TCSS[2:0] bits, and is reloaded with
the value in the reload register when it underflows. Underflows of this register provide the clock source to drive counting
by the TCNT register. The reload register and read buffer are allocated to the same address. Data is written to the reload
register in writing, and the counter value that has been transferred to the read buffer is returned in reading.
It takes one PCLK cycle to load a value from the reload register to the counter.
33.2.39 Timer Count Register (TCNT)
TCNT consists of an 8-bit reload register, a read buffer, and a counter, each of which has FFh as its initial value. This
down-counter counts underflows of the TPRE register until the TCNT register underflows, and is then reloaded with the
value from the reload register. The reload register and read buffer are allocated to the same address. Data is written to the
reload register in writing, and the counter value that has been transferred to the read buffer is returned in reading.
It takes one PCLK cycle to load a value from the reload register to the counter.
Address(es): SCI12.TPRE 0008 B332h
b7 b6 b5 b4 b3 b2 b1 b0
Value after reset:
11111111
Address(es): SCI12.TCNT 0008 B333h
b7 b6 b5 b4 b3 b2 b1 b0
Value after reset:
11111111
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