Renesas RX Series User Manual

R01UH0823EJ0100 Rev.1.00 Page 1620 of 1823
Jul 31, 2019
RX23W Group 45. 12-Bit D/A Converter (R12DAA)
45. 12-Bit D/A Converter (R12DAA)
45.1 Overview
This MCU includes two channels of 12-bit D/A converter.
Table 45.1 lists the specifications of the 12-bit D/A converter and Figure 45.1 shows a block diagram of the 12-bit D/A
converter.
Figure 45.1 Block Diagram of 12-Bit D/A Converter
Table 45.1 Specifications of 12-Bit D/A Converter
Item Specifications
Resolution 12 bits
Output channels Two channels
Measure against mutual interference
between analog modules
Measure against interference between D/A and A/D conversion
D/A converted data update timing is controlled by the 12-bit A/D converter synchronous D/A
conversion enable signal from the 12-bit A/D converter.
Therefore, the degradation of A/D conversion accuracy due to interference is reduced by
controlling the timing in which the 12-bit D/A converter inrush current occurs, with the enable
signal.
Low power consumption function Module stop state can be set.
Event link function (input) DA0 conversion can be started when an event signal is input.
Channel 0
event signal input
12-bit
D/A
Control circuit
12-bit A/D converter
synchronous D/A
conversion enable signal
DAADSCR
DA1
DA0
AVCC0
AVSS0
Bus interface
DADR0 DADR1
DADPR
DACR
DAVREFCR
Synchronization
circuit
Module data bus
Internal
peripheral
bus
DA1
DA0
DADR0: D/A data register 0
DADR1: D/A data register 1
DACR: D/A control register
DADPR: Data register format select register
DAADSCR: D/A A/D synchronous start control register
DAVREFCR: D/A VREF control register

Renesas RX Series Specifications

General

Core	RXv1, RXv2, RXv3
Flash Memory	Up to 8 MB
RAM	Up to 1 MB
Operating Voltage	1.62V to 5.5V
Operating Temperature	-40°C to +85°C or +105°C
Package	BGA, LQFP
ADC Resolution	12-bit
DAC Resolution	12-bit
Communication Interfaces	SCI, SPI, I2C, USB, Ethernet, CAN
Architecture	32-bit
Security Features	Memory Protection Unit (MPU)