Renesas RX Series User Manual

R01UH0823EJ0100 Rev.1.00 Page 1179 of 1823
Jul 31, 2019
RX23W Group 35. I
2
C-bus Interface (RIICa)
35.10.3 Issuing a Stop Condition
The RIIC issues a stop condition when the ICCR2.SP bit is set to 1.
When the SP bit is set to 1, a stop condition issuance request is made and the RIIC issues a stop condition when the
ICCR2.BBSY flag is 1 (bus busy state) and the ICCR2.MST bit is 1 (master mode).
A stop condition is issued in the following sequence.
Stop condition issuance
(1) Drive the SDA0 line low (high level to low level).
(2) Ensure the low-level period of SCL0 line set in the ICBRL register.
(3) Release the SCL0 line (low level to high level).
(4) Detect a high level of the SCL0 line and ensure the time set in the ICBRH register and the stop condition setup time.
(5) Release the SDA0 line (low level to high level).
(6) Ensure the time set in the ICBRL register and the bus free time.
(7) Set the BBSY flag to 0 (to release the bus mastership).
Figure 35.38 Stop Condition Issue Timing (SP Bit)
TRS
STOP
MST
BBSY
IIC
Write 1 to SP bit
ICBRH ICBRL
TDRE
ICBRLICBRH
ACK/NACK
ICBRLICBRH
89 P
Bus free timeSetup time
SP
Set STOP flag to 0
Accept stop condition issuance
Issue stop
condition
ICBRL
b0
SCL0
SDA0

Renesas RX Series Specifications

General

Core	RXv1, RXv2, RXv3
Flash Memory	Up to 8 MB
RAM	Up to 1 MB
Operating Voltage	1.62V to 5.5V
Operating Temperature	-40°C to +85°C or +105°C
Package	BGA, LQFP
ADC Resolution	12-bit
DAC Resolution	12-bit
Communication Interfaces	SCI, SPI, I2C, USB, Ethernet, CAN
Architecture	32-bit
Security Features	Memory Protection Unit (MPU)