R01UH0823EJ0100 Rev.1.00 Page 1194 of 1823
Jul 31, 2019
RX23W Group 36. CAN Module (RSCAN)
36.2.2 Bit Configuration Register H (CFGH)
Modify the CFGH register only in channel reset mode or channel halt mode. Set this register in channel reset mode
before making a transition to channel communication mode or channel halt mode. For setting bit timing, see
section
36.9, Initial Settings
.
TSEG1[3:0] Bits (Time Segment 1 Control)
These bits are used to specify a Tq value for the total length of the propagation time segment (PROP_SEG) and phase
buffer segment 1 (PHASE_SEG1). A value of 4 Tq to 16 Tq can be set.
TSEG2[2:0] Bits (Time Segment 2 Control)
These bits are used to specify a Tq value for the length of phase buffer segment 2 (PHASE_SEG2).
A value of 2 Tq to 8 Tq can be set. Set a value smaller than the value of the TSEG1[3:0] bits.
Address(es): RSCAN0.CFGH 000A 8302h
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
—————— SJW[1:0] — TSEG2[2:0] TSEG1[3:0]
Value after reset:
0000000000000000
Bit Symbol Bit Name Description R/W
b3 to b0 TSEG1[3:0] Time Segment 1 Control
b3 b0
0000:Setting prohibited
0001:Setting prohibited
0010:Setting prohibited
0011:4 Tq
0100:5 Tq
0101:6 Tq
0110:7 Tq
0111:8 Tq
1000:9 Tq
1001:10 Tq
1010:11 Tq
1011:12 Tq
1100:13 Tq
1101:14 Tq
1110:15 Tq
1111:16 Tq
R/W
b6 to b4 TSEG2[2:0] Time Segment 2 Control
b6 b4
0 0 0: Setting prohibited
001:2 Tq
010:3 Tq
011:4 Tq
100:5 Tq
101:6 Tq
110:7 Tq
111:8 Tq
R/W
b7 — Reserved This bit is read as 0. The write value should be 0. R/W
b9, b8 SJW[1:0] Resynchronization Jump Width
Control
b9 b8
00:1 Tq
01:2 Tq
10:3 Tq
11:4 Tq
R/W
b15 to b10 — Reserved These bits are read as 0. The write value should be 0. R/W
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