Renesas RX Series User Manual

R01UH0823EJ0100 Rev.1.00 Page 1569 of 1823
Jul 31, 2019
RX23W Group 44. 12-Bit A/D Converter (S12ADE)
44.2.26 A/D Compare Function Window A Upper-Side Level Setting Register
(ADCMPDR1)
ADCMPDR1 is a readable/writable register that sets the reference data when the compare window A function is used.
ADCMPDR1 sets the upper-side level of window A.
The ADCMPDR1 register is writable even during A/D conversion. The reference data can be dynamically modified by
rewriting register values during A/D conversion.
Set the registers so that the upper-side level is not less than the lower-side level (ADCMPDR1 setting value ≥
ADCMPDR0 setting value).
The ADCMPDR1 register is not used when the window function is disabled.
The ADCMPDR1 register uses different formats depending on the following conditions.
 Settings of the A/D data register format select bit (flush-right or flush-left)
 Settings of the A/D-converted value addition/average function select register (A/D-converted value average mode
selected or not selected)
 Settings of the A/D-converted value addition/average count select register (addition/average mode selected,
addition count selected)
Note: If a format different from the format setting of A/D data register y is used to set the compare value, a correct
comparison result will not be obtained.
(1) When A/D-Converted Value Addition/Average Mode is Not Selected
 Flush-right format
Set bits 11 to 0 to the upper-side comparison level. Write 0 to bits 15 to 12.
 Flush-left format
Set bits 15 to 4 to the upper-side comparison level. Write 0 to bits 3 to 0.
(2) When A/D-Converted Value Average Mode is Selected
 Flush-right format
Set bits 11 to 0 to the upper-side comparison level for comparison with the A/D-converted value of the same
channel. Write 0 to bits 15 to 12.
 Flush-left format
Set bits 15 to 4 to the upper-side comparison level for comparison with the A/D-converted value of the same
channel. Write 0 to bits 3 to 0.
A/D-converted value average mode can be set only when two or four times is selected in A/D-converted value addition
mode.
(3) When A/D-Converted Value Addition Mode is Selected
 Flush-right format (A/D-converted value addition mode and 1-time to 4-time conversion selected)
Set bits 13 to 0 to the upper-side comparison level for comparison with the A/D-converted value of the same
channel. Write 0 to bits 15 and 14.
 Flush-right format (A/D-converted value addition mode and 16-time conversion selected)
Set bits 15 to 0 to the upper-side comparison level for comparison with the A/D-converted value of the same
channel.
Address(es): S12AD.ADCMPDR1 0008 909Eh
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
Value after reset:
0000000000000000

Renesas RX Series Specifications

General

Core	RXv1, RXv2, RXv3
Flash Memory	Up to 8 MB
RAM	Up to 1 MB
Operating Voltage	1.62V to 5.5V
Operating Temperature	-40°C to +85°C or +105°C
Package	BGA, LQFP
ADC Resolution	12-bit
DAC Resolution	12-bit
Communication Interfaces	SCI, SPI, I2C, USB, Ethernet, CAN
Architecture	32-bit
Security Features	Memory Protection Unit (MPU)